Conversly, the apple silicon products ship huge, expensive dies fabbed on leading TSMC processes which sip power relative to contemporaries. You can have excellent power efficiency on a large die at a specific frequency range, moreso than a smaller die clocked more aggressively.
vikingtons
Good to know, that's not the one I had in mind, however.
For whatever reason I thought PMOS was based on Manjaro. Could be something as silly as associating one green logo with another.
As much as I want that to be the case, I don't think full mobile gnu+Linux is really ready to use daily?
I haven't exactly been keeping up with things, mind you
Would it almost be equivalent to snap on Android?
I've heard very little about it. Is there some controversy around it?
waiting to see it ported to the HTC hd2
This video is so fucking funny I didn't care that it's almost four hours long lmao
What I was alluding to with regards to idle mclk behaviour is that there are two factors at play: vertical balanking interval (intrinsic to available display modes for each physical monitor) and combined display bandwidth (cumulative of all connected displays to the adapter).
Your mclk will idle high with 'incompatible' VBIs, and it'll also idle high to sustain a lot of display throughput.
This can be observed regardless of GFX vendor, though symptoms may vary somewhat between them. I suppose it could be considered a limitation of GDDR (the same behaviour was never really observed on HBM GPUs like the Vega 64 or Radeon VII)
That said, friends of mine with nvidia gpus have fixed various multi-display specific issues using nvidia profile inspector
I don't know if it was a bug so much as a deficiency. OS Improvements to branch prediction will most likely not be backported to Win10
I don't think this is related to the OS. What displays do you have connected?
It's like that episode of futurama - the mirror wernstrom put in space to reflect sunlight, which gets tapped by a little space rock, and tilts into a solar powered death beam
This outlines several issues, a key one is outbidding apple for wafer alloc on leading processes. They primarily sell such high margin products that I suppose they can go full send on huge dies with no sweat. Similarly, the 4090's asking price was likely directly related to it's production cost. A chunky boy with a huge l2$.
I like the way Mike Clark frames challenges in semi eng as a balancing act between area, power, freq and performance (IPC); like a chip that's twice as fast but twice the size of its predecessor is not considered progress.
I wish ultra-efficient giga dies were more feasible but it's kind of rough when TSMC has been unmatched for so long. I gather Intel's diverting focus in 18A, and I hope that turns out well for them.
I'm not sure that arm as an ISA (or even RISC) is inherently more efficient than CISC today, particularly when we look at Qualcomm's latest efforts in notebooks, more that Apple have extremely proficient designers and benefit from vertical integration.