hardware26

cross-posted from: https://discuss.tchncs.de/post/8824219

One way to help alleviate the effects of the talent shortage is changing how semiconductors are designed so that organizations can achieve more with their existing workforce. This requires moving away from project-centric design and transitioning to an IP-centric design methodology.

Over the past few years, teams have moved from building relatively self-contained, isolated designs to creating complex platforms across dispersed and integrated design centers. Larger design footprints, a more comprehensive array of products and quicker time to market are other contributing factors to walking away from a project-based design methodology.

cross-posted from: https://discuss.tchncs.de/post/3979328

Engineers in Princeton managed to train GPT4 and extend AutoSVA to generate SVA (systemverilog assertions) from buggy RTL and functionality description. SVA is widely used to verify digital design for ASIC and FPGAs. AutoSVA2, which extends open-source AutoSVA, improves the flow to generate SVA from English description. LLM was trained in multiple iterations to generate SVA with correct syntax, which is something GPT fails to do by itself. Authors argue that GPT's "creativity" allows it to write correct assertion even from a buggy RTL. Later authors used this tool to write RTL from scratch as well. RTL written by GPT was tested against the SVA generated by this tool, and SVA corrected by an engineer was fed back to LLM, which generated functionally correct FIFO queue in a few iterations.

Abstract—Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as SystemVerilog Assertions (SVA), are time-consuming and error- prone to write, even for experienced users. Prior work has attempted to lighten this burden by raising the abstraction level so that SVA is generated from high-level specifications. However, this does not eliminate the manual effort of reasoning and writing about the detailed hardware behavior. Motivated by the increased need for FPV in the era of heterogeneous hardware and the advances in large language models (LLMs), we set out to explore whether LLMs can capture RTL behavior and generate correct SVA properties. First, we design an FPV-based evaluation framework that measures the correctness and completeness of SVA. Then, we evaluate GPT4 iteratively to craft the set of syntax and semantic rules needed to prompt it toward creating better SVA. We extend the open-source AutoSVA framework by integrating our improved GPT4-based flow to generate safety properties, in addition to facilitating their existing flow for liveness properties. Lastly, our use cases evaluate (1) the FPV coverage of GPT4-generated SVA on complex open-source RTL and (2) using generated SVA to prompt GPT4 to create RTL from scratch. Through these experiments, we find that GPT4 can generate correct SVA even for flawed RTL—without mirroring design errors. Particularly, it generated SVA that exposed a bug in the RISC-V CVA6 core that eluded the prior work’s evaluation.

The key takeaway here is that the people writing these guidelines try to give as much information as possible,” Reaves says. “That’s great, in theory. But the writers don’t prioritize the advice that’s most important. Or, more specifically, they don’t deprioritize the points that are significantly less important. And because there is so much security advice to include, the guidelines can be overwhelming – and the most important points get lost in the shuffle.

In other words, the guideline writers are compiling security information, rather than curating security information for their readers.

Drawing on what they learned from the interviews, the researchers developed two recommendations for improving future security guidelines.

First, guideline writers need a clear set of best practices on how to curate information so that security guidelines tell users both what they need to know and how to prioritize that information.

Second, writers – and the computer security community as a whole – need key messages that will make sense to audiences with varying levels of technical competence.

“Look, computer security is complicated,” Reaves says. “But medicine is even more complicated. Yet during the pandemic, public health experts were able to give the public fairly simple, concise guidelines on how to reduce our risk of contracting COVID. We need to be able to do the same thing for computer security.”

cross-posted from: https://discuss.tchncs.de/post/3306215

Although you are probably not aware of them, dozens of electronic control units (ECUs) — printed circuit boards (PCBs) in metal or plastic housings — exist in your car to control and monitor the operation and safety of your vehicle’s many control systems. These units must work for the lifetime of your car, during which time they are subjected to many heating and cooling cycles. The most obvious cycle occurs when you start your car after it has cooled at night. It heats up as the car runs and then cools again when you shut it off. That’s one “ambient” temperature cycle.

Additional so called “active” thermal cycles can occur locally within specific electronic components on the PCB. For instance, a MOSFET transistor draws a lot of current and heats up the PCB near its location, causing additional thermal cycling. These complex temperature distributions can cause local thermomechanical strain because differences in temperature across the PCB result in differential expansion of the board. Because the board is constrained by its housing, this can lead to bending of the board, putting additional strain on the solder joints that connect the components to the board.

The widely used power law based approach — simulation of only few cycles and prognosis of solder joints lifetime — has many shortcomings, where no absolute lifetime prediction or the damage driven load relocation and its nonlinear evolution are captured. Youssef Maniar and Marta Kuczynska, engineers at Robert Bosch GmbH in Germany, have developed an accurate nonlinear damage model able to predict absolute lifetime of solder connections. The problem they faced, absolute lifetime prediction, involves simulation of all cycles imposed to the components, and the computational effort is therefore extensive. Then, about two years ago, they read an academic paper that described a way to “jump” over some cycles to accelerate simulation.

The mathematics behind the ability to jump over a large number of simulated thermomechanical cycles to dramatically accelerate the simulation time without sacrificing accuracy is involved, but the software essentially looks at the slope or “gradient” of certain solution variables (e.g., stress) versus time plot on the fly to determine when it can skip over the next n number of cycles. The maximum value of n must be defined by the simulation engineer before the run. The simulation engineer also inputs other parameters beforehand to impose limits on the software to optimize the run.

cross-posted from: https://discuss.tchncs.de/post/3011500

Many volume applications use FPGA because they need in-field reconfigurability (changing standards, changing algorithms, etc) but they want to improve their system’s competitiveness (power, size, cost). FPGAs are bulky, expensive and power hungry. Integrating eFPGA can greatly improve the economics while maintaining full reconfigurability and performance.

We’ve found with customers that a significant portion of the LUTs in their designs don’t change with reconfigurations: they are fixed buses to bring data to and from the reconfigurable core. This can be hardwired so the number of LUTs needed in the SoC is typically half of what’s in the FPGA. There is also a lot of cost of voltage regulators for an FPGA that disappear with integration.

Typically, the cost of eFPGA is 1/10th the cost of the FPGA it replaces but with the same speed and programmability. Power can also be cut to 1/10th because most of the power in an FPGA is the power-hungry PHYs that are mostly not needed when using eFPGA in the SoC.

In a study recently published in the journal Patterns, researchers demonstrate that computer algorithms often used to identify AI-generated text frequently falsely label articles written by non-native language speakers as being created by artificial intelligence. The researchers warn that the unreliable performance of these AI text-detection programs could adversely affect many individuals, including students and job applicants.

cross-posted from: https://discuss.tchncs.de/post/2739005

https://semiengineering.com/challenges-in-ramping-new-manufacturing-processes/

Despite a slowdown for Moore’s Law, there are more new manufacturing processes are rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks about the various steps involved in determining what can be printed on a wafer, how to reduce defect density, and what other concerns need to be addressed to ramp a new process.

The genesis of this upheaval is inextricably tied to the smart phone revolution. “It was when people realized what the phone could do for their life,” Curran said. “That led people to ask why their car was not able to know them and understand what they want. ‘Why do I have all these buttons? Why isn’t it upgradable like the phone is upgradable?’ Then, when Tesla came out and started the whole vehicle based on the software, people realized this is the way of the future.

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For automotive OEMs to adopt new architectures requires a fundamental shift in how they approach their supply chain. Modules cannot be developed individually by multiple Tier 1 and Tier 2 suppliers. Instead, they need to be developed in sync, with an understanding of how each is characterized and how they can be fully integrated. “You can’t have Bosch do one module, Continental do another module, Aptiv do a separate module, then plug them in on the assembly line and think the experience is going to be great,” she said.

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“The OEMs are saying, ‘If I’m going to go to 3nm, which is $75 million to $100 million for a mask set, plus a huge development team, where am I going to get those people? That’s not the biggest pool of talent in the world,” said Fritz. “‘How do I do that?’ Chiplets. So now they’re saying, ‘I can have these companies, maybe even startups, developing a chiplet.’ It’s more cost-effective for them, because those chiplets can be sold to many customers and across multiple market segments and get the volume up.

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“An application like Apple CarPlay is different from other components in a vehicle, where others are trying to collaborate as OEMs pull it together,” said Simon Rance, director, product management, data & IP management at Keysight EDA. “The user experience plays a big role in the outcome of that design and application. That’s where there needs to be tighter collaboration between those OEMs that are involved in that system, not just Apple with the CarPlay app and its capabilities and functions. How does it interface with Bluetooth? How does it interface with sensors and sensor data, for example? These are where vendors are looking to take these capabilities, or solutions like CarPlay, to the next level.

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"We’ve had these traditional collaborations in automotive where we get OEM cross-synchronization,” Lapides said. “Traditionally that’s been around AUTOSAR, maybe around embedded Linux, and certainly around overall SoC design. But now we’re seeing much more collaboration in the software area, outside of AUTOSAR, outside of the OS. We’re seeing more collaboration getting down to the processor side and what the processor can do. Those things are really interesting — especially in automotive, where AI is going out to the edge with sensors.

cross-posted from: https://discuss.tchncs.de/post/2554454

The digital RAKs provide Arm Neoverse V2 designers with several key benefits. For example, the Cadence Cerebrus AI capabilities automate and scale digital chip design, delivering better PPA and improving designer productivity. Cadence iSpatial technology provides an integrated and predictable implementation flow for the faster design closure. The RAKs also include a smart hierarchy flow that delivers optimal turnaround times on large, high-performance CPUs. The Tempus ECO technology offers signoff-accurate final design closure based on path-based analysis. Finally, the RAKs incorporate the GigaOpt activity-aware power optimization engine to significantly reduce dynamic power consumption.