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China’s push for chip independence continues with its first RISC-V server CPU (www.tomshardware.com)

submitted 3 weeks ago by [email protected] to c/[email protected]

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cross-posted from: https://lemmy.zip/post/35528933

China is doubling down on the RISC-V architecture.

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[–] [email protected] 5 points 3 weeks ago

great reply. I am not saying RISC is the panecea, what I am saying is that there are more options for workload optimization further up the stack and rebalancing of the intelligence from the silicon to the software is an advantage.

some time ago most CISC core design become more RISC-y and, to indulge in some ISA snobbery, I just want to slash and burn the CISC presentation to the software layer. memory is cheap, bus bandwidth is insane - simplification on the ISA just seems like a hardware complexity win all around and I am willing to pay for that in compiler complexity that incorporates changes more easily than hardware or CISC microcode.

RISC-V's challenge is can they standardise the software ecosystem enough[...]

agreed. this is why I say my wait may be coming to an end.

personally, I think RISC is the more flexible design in almost every usecase. cycle for cycle, RISC hits the right buttons for me across the widest number of situations once we get above the "magic hardware" layer. willing to flog the CISC vs RiSC horse convo if you have recent information, and thanks for the response.