Technology

68306 readers

4439 users here now

This is a most excellent place for technology news and articles.

Our Rules

Follow the lemmy.world rules.
Only tech related news or articles.
Be excellent to each other!
Mod approved content bots can post up to 10 articles per day.
Threads asking for personal tech support may be deleted.
Politics threads may be removed.
No memes allowed as posts, OK to post as comments.
Only approved bots from the list below, this includes using AI responses and summaries. To ask if your bot can be added please contact a mod.
Check for duplicates before posting, duplicates may be removed
Accounts 7 days and younger will have their posts automatically removed.

Approved Bots

founded 2 years ago

MODERATORS

[email protected]

270

China’s push for chip independence continues with its first RISC-V server CPU (www.tomshardware.com)

submitted 1 day ago by [email protected] to c/[email protected]

34 comments fedilink hide all child comments

cross-posted from: https://lemmy.zip/post/35528933

China is doubling down on the RISC-V architecture.

you are viewing a single comment's thread
view the rest of the comments

[–] [email protected] 4 points 1 day ago

great reply. I am not saying RISC is the panecea, what I am saying is that there are more options for workload optimization further up the stack and rebalancing of the intelligence from the silicon to the software is an advantage.

some time ago most CISC core design become more RISC-y and, to indulge in some ISA snobbery, I just want to slash and burn the CISC presentation to the software layer. memory is cheap, bus bandwidth is insane - simplification on the ISA just seems like a hardware complexity win all around and I am willing to pay for that in compiler complexity that incorporates changes more easily than hardware or CISC microcode.

RISC-V's challenge is can they standardise the software ecosystem enough[...]

agreed. this is why I say my wait may be coming to an end.

personally, I think RISC is the more flexible design in almost every usecase. cycle for cycle, RISC hits the right buttons for me across the widest number of situations once we get above the "magic hardware" layer. willing to flog the CISC vs RiSC horse convo if you have recent information, and thanks for the response.