270
China’s push for chip independence continues with its first RISC-V server CPU
(www.tomshardware.com)
this post was submitted on 03 Apr 2025
270 points (97.5% liked)
Technology
68306 readers
4439 users here now
This is a most excellent place for technology news and articles.
Our Rules
- Follow the lemmy.world rules.
- Only tech related news or articles.
- Be excellent to each other!
- Mod approved content bots can post up to 10 articles per day.
- Threads asking for personal tech support may be deleted.
- Politics threads may be removed.
- No memes allowed as posts, OK to post as comments.
- Only approved bots from the list below, this includes using AI responses and summaries. To ask if your bot can be added please contact a mod.
- Check for duplicates before posting, duplicates may be removed
- Accounts 7 days and younger will have their posts automatically removed.
Approved Bots
founded 2 years ago
MODERATORS
you are viewing a single comment's thread
view the rest of the comments
view the rest of the comments
Do you have any resources by any chance that explain the difference well?
I work in high level software, so understand the benefit of doing things at ide time vs compile time vs runtime, and I've coded in assembly back in the day and understand instruction sets at a very rough level, but I'm not really familiar with specifically what differentiates RISC / ARM / x64, or why RISC's reductions would be good / bad / what trade-offs come with them.
between the 30k' overview of Reduced instruction set computer (RISC) architecture and the lower level RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA, you should get a pretty decent feel for it.
the level of optimization you get via hardware and software tooling is honestly pretty spectacular. I have been waiting for RISC to come out of hiding for years and it seems to be happening.