this post was submitted on 24 Nov 2023
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Now ask open AI to type for you what the draw backs of FPGA is. Also the newest slew of chips is using partially charged NAND gates instead of FPGA.
Almost all ASIC being used right now is implementing the basic math functions, activations, etc. and the higher level work is happening in more generalized silicon. You can not get the transistor densities necessary for modern accelerator work in FPGA.
Friend, I do this for a living, and I have no idea why you're even bringing gating into the equation, because it doesn't even matter.
I'm assuming you're a big crypto fan, because that's about all I could say of ASIC in an HPC type of environment to be good for. Companies who pay the insane amounts of money for "AI" right now want a CHEAP solution, and ASIC is the most short-term, e-wastey, inflexible solve to that problem. When you get a job in the industry and understand the different vectors, let's talk. Otherwise, you're just spouting junk.
Swing and a miss.
Really? Gee, I think switching fabrics might have a thing to tell you. For someone that does this for a living, to not know the extremely common places that ASICs are used is a bit of a shock.
Yeah, I already covered that in my initial comment, thanks for repeating my idea back to me.
Literally being atabled to the Intel tiles in Sapphire Rapids and beyond. Used in every switch, network card, and millions of other devices. Every accelerator you can list is an ASIC. Shit, I've got a Xilinx Alveo 30 in my basement at home. But yeah, because you can get an FPGA instance in AWS, you think you know that ASICs aren't used. lmao
I've got bad news for you about ML as a whole.
Sometimes the flexibility of a device's application isn't the device itself, but how it's used. Again, if I can do thousands, tens of thousands, or hundreds of thousands of integer operations in a tenth of the power, and a tenth of the clock cycles, then load those results into a segment of activation functions that can do the same, and all I have to do is move this data with HBM and perhaps add some cheap ARM cores, bridge all of this into a single SoC product, and sell them on the open market, well then I've created every single modern ARM product that has ML acceleration. And also nvidia's latest products.
Woops.
I've been a hardware engineer for longer than you've been alive, most likely. I built my first FPGA product in the 90s. I strongly suspect you just found this hammer and don't actually know what the market as a whole entails, let alone the long LONG history of all of these things.
Do look up ASICs in switching, BTW. You might learn something.
You're such a dick for no reason. It definitely bolsters your claims your an old school tech guy lol
Not for no reason. They made claims, I provided links, they whined about it. They provided zero links backing up their 40 year old claim that FPGA would replace anything that didn't run away fast enough.